This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-313939 filed on Oct. 11, 2001, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The invention relates to a semiconductor device, a method of manufacturing such a semiconductor device, and a system for evaluating electrical characteristics of the semiconductor device. Particularly, the invention relates to a semiconductor device which is preferable to evaluating time-dependent degradations of electrical characteristics of a semiconductor element, a method of manufacturing such a semiconductor device, and an electrical characteristics evaluating system.
2. Description of the Related Art
It is well-known that a MOSFET (metal oxide semiconductor field effect transistor) such as a silicon element varies its electrical characteristics with time. Generally speaking, electrical characteristics of a semiconductor device become worse with a lapse of time. The semiconductor device is required to remain reliable for a long period of time like 10 or 20 years during the normal use. In other words, the semiconductor device should maintain its electrical characteristics within a product specification limit even when they are degraded during the use.
It is empirically known that degradations of electrical characteristics of the MOSFET are predictable by monitoring a substrate current. For example, refer to C. Hu et al. xe2x80x9cHot-Electron-Induced MOSFET Degradation-Model, Monitor and Improvementxe2x80x9d (IEEE Transactions on Electron Devices, Vol. ED-32, 1985). This reference describes that degradations of electrical characteristics depend upon the substrate current as follows. Some hot carriers which are given energy by a electric field tend to damage a gate insulated film or the like, form levels in an interface of the gate insulated film, and are trapped in the gate insulated film, thereby degrading electrical characteristics of the semiconductor element.
Further, hot carriers in a semiconductor substrate cause impact ionization therein. Then, electron hole pairs will be generated. Charges which are opposite to those constituting a channel flow through the semiconductor substrate as a substrate current. For instance, in the case of an n-channel conductivity type MOSFET, charges constituting the channel are electrons, so that the holes flow through the semiconductor substrate as a substrate current. In short, the degradations of electrical characteristics and the substrate current are caused by the carriers of the high energy condition in the MOSFET. For this reason, it is predictable that the degradations of electrical characteristics of the MOSFET and the substrate current are correlated. The relation has been empirically established between the degradations of electrical characteristics and the substrate current. Therefore, it is possible to predict the degraded electrical characteristics of the MOSFET by monitoring the substrate current.
Generally, semiconductor elements whose electrical characteristics extensively degrade during the initial stage of use tend to maintain the initially degraded state. Conversely, semiconductor elements having excellent electrical characteristics at the initial stage, i.e. semiconductor elements having a high current value, tend to extensively degrade during the use because they tend to have the carriers of the high energy condition. In other words, initial electrical characteristics and degradation resistance are contradictory with each other. It is natural to manufacture semiconductor devices having excellent initial electrical characteristics taking the degradation resistance into consideration. Such semiconductor devices should have electrical characteristics defined by their specification with respect to the lifetime expectancy. In short, if a semiconductor device has excessively long life, it means that its electrical characteristics may be sacrificed.
It is therefore very important to evaluate the degradations of electrical characteristics when manufacturing semiconductor devices. The degradations of electrical characteristics of the semiconductor device are evaluated by monitoring the degradation of electrical characteristics when stress of direct current (DC stress) is applied to a semiconductor element. For instance, the degradations of electrical characteristics after an electronic circuit is assumed to be used for ten years are evaluated as follows. A dynamic stress which varies with time is primarily applied to a semiconductor element for constituting an electronic circuit. The degradations of electrical characteristics are evaluated assuming that a half of the whole DC stress for ten years is applied to the semiconductor element (The approach of xe2x80x9cduty factorxe2x80x9d.), and that electrical characteristics of the semiconductor element are degraded to a level in which the DC stress has been applied for five years. This evaluation is performed on the basis of the degradation of electrical characteristics due to the DC stress although the dynamic stress is primarily applied to the semiconductor element. Therefore, the foregoing evaluation method cannot be always precise.
On the contrary, the BERT (Berkeley Reliability Tool) developed by University of California at Berkeley, U.S.A. uses the circuit simulation technique in order to reliably evaluate the degradations of electrical characteristics of a semiconductor device as described hereinafter.
First of all, a dynamic circuit simulation is performed for a semiconductor element which is free from any degradation of electrical characteristics. A substrate current or the like of the semiconductor element which constitutes a circuit and is in a dynamic state is calculated as a function of time. For instance, the degradations of electrical characteristics of the semiconductor element in a certain time period are evaluated on the basis of the relationship between a time integral of physical quantities including a calculated substrate current Isub(t), and an empirically created relationship between the substrate current and degradations of electrical characteristics.             (                                    I            sub                    ⁢                      (            t            )                                    Id          ⁢                      (            t            )                              )        α    ⁢            Id      ⁡              (        t        )              β  
where Id denotes a drain current, and xcex1 and xcex2 denote model parameters.
Degraded electrical characteristics of the circuit are evaluated on the basis of degradations of electrical characteristics of the semiconductor element derived using the foregoing process.
This method is effective in evaluating the degraded electrical characteristics of the semiconductor element taking dynamic stresses into consideration, and is more reliable than the evaluation method using the DC stress.
However, the foregoing evaluation methods seem to have the following problems.
(1) In the foregoing circuit simulation, the influence of the semiconductor element which constitutes a circuit in operation and is in non-equilibrium cannot be precisely taken into consideration. For instance, it is well-known that carrier energies in a semiconductor element are in non-equilibrium in the following semiconductor elements: a semiconductor element whose channel length is short compared with an mean free path of carriers; a semiconductor element in which an electric field varies very steeply; a semiconductor element to which a voltage is applied and in which an electric field steeply varies with time, or the like. The electrical characteristics of such semiconductor elements cannot be precisely evaluated through the circuit simulation, and a substrate current cannot be correctly calculated. Therefore, the degradations of electrical characteristics cannot be precisely evaluated.
(2) In a semiconductor device in which polycrystalline silicon is used as a semiconductor active region and a semiconductor element is formed in the semiconductor active region, carriers in the semiconductor active region have short lifetimes. In other words, electron hole pairs caused by impact ionization are excessively recombined in the semiconductor active region, and most of them disappear due to recombination, so that only part of generated carriers are observed as a substrate current. In such a semiconductor element, the substrate current is no longer an index representing the carriers of the high energy condition in the semiconductor region, so that no correlation can be usually established between the substrate current and the degradation of electrical characteristics. Therefore, the degradations of electrical characteristics of the semiconductor element cannot be precisely evaluated on the basis of the substrate current even when the circuit simulation is performed.
(3) No substrate current is present in a semiconductor device having the SOI (silicon-on-insulator) structure in which a semiconductor element is formed in a semiconductor active region which is made of single crystal silicon and is provided on a silicon substrate via a silicon oxide film. This is because there is no substrate electrode. Therefore, the degradation of electrical characteristics cannot be evaluated since no substrate current can be calculated even if the circuit simulation is performed.
According to a first aspect of the invention, there is provided a method of manufacturing a semiconductor device, comprising: forming a semiconductor element in a semiconductor active region, and calculating the generation rate of electron hole pairs caused by impact ionization in the semiconductor element; calculating a volume integral of the generation rate of electron hole pairs at least in an area where the impact ionization is caused; evaluating time-dependent variations of electrical characteristics of the semiconductor element on the basis of the volume integral; and manufacturing a semiconductor device on the basis of evaluation results.
In accordance with a second aspect of the invention, there is provided a method of manufacturing a semiconductor device, comprising: forming a semiconductor element in a semiconductor active region, and calculating the generation rate of electron hole pairs caused by impact ionization in the semiconductor element; calculating a volume integral of the generation rate of electron hole pairs at least in an area where the impact ionization is caused; calculating a time integral of physical quantities including the volume integral; evaluating time-dependent variations of electrical characteristics of the semiconductor element on the basis of the time integral; and manufacturing a semiconductor device on the basis of evaluation results.
According to a third aspect of the invention, there is provided a method of manufacturing a semiconductor device, comprising: forming a first insulated gate field effect transistor having a body contact electrode in a first semiconductor active region on an insulated layer at least on a substrate, measuring at least a body current of the first semiconductor active region and creating data concerning at least the body current; forming a second insulated gate field effect transistor without a body contact electrode in a second semiconductor active region on the insulated film layer, and calculating the generation rate of electron hole pairs caused by impact ionization in the second insulated gate field effect transistor; calculating a volume integral of the generation rate of electron hole pairs at least in a region where impact ionization is caused; calculating time-dependent variations of electrical characteristics of the second insulated gate field effect transistor on the basis of the volume integral and at least the body current in the data; and manufacturing a semiconductor device on the basis of the calculated time-dependent variations of electrical characteristics.
With a fourth aspect of the invention, there is provided a method of manufacturing a semiconductor device, comprising: performing initial designing of a semiconductor element to be formed in a semiconductor active region; calculating the generation rate of electron hole pairs caused by impact ionization in the semiconductor element; calculating a volume integral of the generation rate of electron hole pairs at least in a region where the impact ionization is caused; evaluating time-dependent variations of electrical characteristics of the semiconductor element on the basis of the volume integral; and redesigning the semiconductor element on the basis of evaluation results.
According to a fifth aspect of the invention, there is provided a method of manufacturing a semiconductor device, comprising: forming a semiconductor element in a semiconductor active region and calculating the generation rate of electron hole pairs caused by impact ionization in the semiconductor element; calculating a volume integral of the generation rate of electron hole pairs at least in a region where the impact ionization is caused; calculating a physical model quantity after application of stresses to the semiconductor element, on the basis of the volume integral; evaluating time-dependent variations of electrical characteristics after application of stress to the semiconductor element, on the basis of the calculated physical model quantity; and manufacturing a semiconductor device on the basis of evaluation results.
In accordance with a sixth aspect of the invention, there is provided a semiconductor device comprising: a substrate provided with an insulated layer at least on a surface thereof; a first semiconductor active region on the insulated layer of the substrate; a first insulated gate field effect transistor formed in the first semiconductor active region, provided with a body contact electrode and used for detecting a body current; a second semiconductor active region on the insulated layer of the substrate; and a second insulated gate field effect transistor formed in the second semiconductor active region and having no body contact electrode.
According to a seventh aspect of the invention, there is provided an electrical characteristic evaluating system comprising: a data inputting unit inputting physical model quantity data of a semiconductor element; a data processing unit calculating on the basis of the input data the generation rate of electron hole pairs caused by impact ionization in the semiconductor element, calculating a volume integral of the generation rate of electron hole pairs at least in a region where the impact ionization is caused, and calculating time-dependent variations of the semiconductor element at least on the basis of the volume integral; and a data outputting unit for outputting the calculated time-dependent variations of electrical characteristics.